ABSTRACT
Hyper Transport chip-to-chip interconnect technology is a highly optimized, high performance and low latency board-level architecture for embedded and open- architecture systems. . It provides up to 22.4 Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth in a highly efficient chip-to-chip technology that replaces existing complex multi-level buses. . In addition to delivering the industry's highest bandwidth, frequency scalability, and lowest implementation cost, the technology is software compatible with legacy Peripheral Component Interconnect (PCI) and PCI -X and emerging PCI Express technologies.
Hyper Transport technology delivers very high data rate and bandwidth by means of easy-to-implement Low Voltage Differential Signaling (LVDS) and point-to-point links. Hyper Transport isn't just a new bus implementation that's a little faster than its predecessors. It's whole new bus architecture, designed to grow over time. Surely future will see the rapid advancement of Hyper Transport technology.
Ps : Including PPT
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